Hardware Acceleration in Genode OS Using Dynamic Partial Reconfiguration

Algorithms with operations on large regular data structures such as image processing can be highly accelerated when executed as hardware tasks in an FPGA fabric. The Dynamic Partial Reconfiguration (DPR) feature of new SRAM-based FPGA families allows a dynamic swapping and replacement of hardware tasks during runtime. Particularly embedded systems with processing chains that change over time or that are too large to be implemented in an FPGA fabric in parallel, benefit from DPR. In this paper we present a complete framework for hardware acceleration using DPR in the microkernel based Genode OS. This makes the DPR feature available not only for the high-performance computing field, but also for safety-critical applications. The new framework is evaluated for an exemplary imaging application running on a Xilinx Zynq-7000 SoC

Self-Adaptation for Availability in CPU-FPGA Systems Under Soft Errors

We introduce a model-based reliability estimation to preserve application availability in CPU-FPGA systems exposed to soft errors under varying environment conditions. The estimation is used as an in-system method to select a suitable configuration for changing radiation conditions. This allows systems to autonomously adapt their configuration in order to balance between reliability and performance. Such a self-adaptation goes beyond the state-of-the-art, where adaptation relies on preplanned reactive mode changes. By autonomously evaluating new configurations, our self-adaptation process is capable of increasing the availability by selecting the configuration with the desired application reliabilities for the current environment conditions

SEU fault classification by fault injection for an FPGA in the space instrument SOPHI

Fault injection through partial dynamic reconfiguration can simulate upsets in configuration memory of SRAM-based FPGAs. FT-UNSHADES 2 is an automated set-up, which runs multiple fault injection campaigns in batch mode, while automatically applying stimuli and comparing output vectors. This work presents the results of fault injection runs of an FPGA design intended for the data processing unit (DPU) of the Solar Orbiter Polarimetric and Helioseismic Imager (SoPHI) instrument on solar orbiter. In this DPU SRAM FPGAs are connected to a processor through a radiation hardened antifuse FPGA. This antifuse FPGA houses the configuration and data interfaces to the SRAM FPGAs of the DPU. When radiation induced errors occur in the SRAM FPGA, the antifuse FPGA isolates these errors and recovers operation. The fault injection campaign gave insight on fault induced behavior on the interfaces of the SRAM FPGA, allowed to categorize them, and create statistics of the different categories. This paper describes the mechanisms of fault detection isolation and recovery in the SRAM/antifuse FPGA interfaces and tests them with the faulty output vectors from fault injection

ECC Memory for Fault Tolerant RISC-V Processors

Numerous processor cores based on the popular RISC-V Instruction Set Architecture have been developed in the past few years and are freely available. The same applies for RISC-V ecosystems that allow to implement System-on-Chips with RISC-V processors on ASICs or FPGAs. However, so far only very little concepts and implementations for fault tolerant RISC-V processors are existing. This inhibits the use of RISC-V for safety-critical applications (as in the automotive domain) or within radiation environments (as in the aerospace domain). This work enhances the existing implementations Rocket and BOOM with a generic Error Correction Code (ECC) protected memory as a first step towards fault tolerance. The impact of the ECC additions on performance and resource utilization are discussed

Generalizability of an Identification Approach for Machine Control Signals in Brownfield Production Environments

Digital transformation has been a central aspect of optimizing processes in manufacturing companies for several years now. A basic prerequisite of successful transformation is the vertical integration of all machines and machine tools to capture data at all levels. This can create further applications that enable more sustainable and resource-saving processes. At the same time cost- and quality-optimizing analyses such as failure detection, predictive maintenance or general process optimization represent major incentives for companies. While the necessary interfaces are now integrated in state-of-the-art machine tools, companies with older legacy machines face the problem that no such interfaces are readily available. Brownfield machine tools feature outdated technology that does not allow direct networking connectivity without further effort. To participate in the technological progress, a system was developed that allows to extract machine control signals from machine tools and identify them automatically as time series. This is compatible with several communication protocols (e.g., OPC UA) to be as universally applicable as possible. Since machine control signals are often not interpretable for the user due to different naming conventions, the extracted time series are analyzed by machine learning and analytical rule bases, these are based on expert knowledge, and assign a specific signal type in each case. With regard to a cross-machine generalization capability, several aspects have to be considered. Due to different data sources, the identification system must still function reliably with varying sampling frequency. Another challenge is the diversity of different types of machines and production equipment. Therefore, this publication investigates the different influences of data sources and machine types on the machine control signal identification system

Resource-efficient dynamic partial reconfiguration on FPGAs for space instruments

Field-Programmable Gate Arrays (FPGAs) provide highly flexible platforms to implement sophisticated data processing for scientific space instruments. The dynamic partial reconfiguration (DPR) capability of FPGAs allows it to schedule HW tasks. While this feature adds another dimension of processing power that can be exploited without significantly increasing system complexity and power consumption, there are still several challenges for an efficient DPR use. State-of-the-art concepts concentrate either on resource-efficient implementations at design time or flexible HW task scheduling at runtime. In this paper we propose a balanced algorithm that considers both optimization goals and is well suited for resource-limited space applications

Demonstrating Controlled Change for Autonomous Space Vehicles

Recent research discusses concepts of infield changes to overcome the drawbacks of conventional lab-based system design processes. In this paper, we evaluate the concept of controlled change by applying it to a demonstration of a potential future space exploration scenario with mobile robots. The robots are capable of executing several image computations for exploration, object detection and pose estimation, which can be allocated to both FPGA-and processor resources of a System-on-Chip. The demonstrator addresses three scenarios which cover application-, environment-, and platform change. The system adapts itself to any of the named changes. This capability can increase the autonomy of future space missions. Exemplary, the demonstrator executes adaption of applications during operation to fulfill the mission goals, adaption of reliability under changing environment conditions, and adaption to sensor failure

Hardware and Software Task Scheduling for ARM-FPGA Platforms

ARM-FPGA coupled platforms allow accelerating the computation of specific algorithms by executing them in the FPGA fabric. Several computation steps of our case study for a stereo vision application have been accelerated by hardware implementations. Dynamic Partial Reconfiguration places these hardware tasks in the programmable logic at appropriate times. For an efficient scheduling, it needs to be decided when and where to execute a task. Although there already exist hardware/software scheduling strategies and algorithms, none exploit all possible optimization techniques: re-use, prefetching, parallelization, and pipelining of hardware tasks. The scheduling algorithm proposed in this paper takes this into account and optimizes for the objectives latency/throughput and power/energy

A comparative survey of open-source application-class RISC-V processor implementations

Revision notice: This version does not contain CVA6 SPEC CPU2017 scores. There is an updated version available with additional CVA6 SPEC CPU2017 scores: https://doi.org/10.24355/dbbs.084-202105101615-

A comparative survey of open-source application-class RISC-V processor implementations

The numerous emerging implementations of RISC-V processors and frameworks underline the success of this Instruction Set Architecture (ISA) specification. The free and open source character of many implementations facilitates their adoption in academic and commercial projects. As yet it is not easy to say which implementation fits best for a system with given requirements such as processing performance or power consumption. With varying backgrounds and histories, the developed RISC-V processors are very different from each other. Comparisons are difficult, because results are reported for arbitrary technologies and configuration settings. Scaling factors are used to draw comparisons, but this gives only rough estimates. In order to give more substantiated results, this paper compares the most prominent open-source application-class RISC-V projects by running identical benchmarks on identical platforms with defined configuration settings. The Rocket, BOOM, CVA6, and SHAKTI C-Class implementations are evaluated for processing performance, area and resource utilization, power consumption as well as efficiency. Results are presented for the Xilinx Virtex UltraScale+ family and GlobalFoundries 22FDX ASIC technology